The ARM Neoverse is a group of 64-bit ARM processor cores licensed by Arm Holdings. The cores are intended for datacenter, edge computing, and high-performance computing use. The group consists of ARM Neoverse V-Series, ARM Neoverse N-Series, and ARM Neoverse E-Series.[1][2]
Neoverse V-Series
editThe Neoverse V-Series processors are intended for high-performance computing.
Neoverse V1
editNeoverse V1 (code named Zeus[3]) is derived from the Cortex-X1[4] and implements the ARMv8.4-A instruction set and some part of ARMv8.6-A.[5] It was officially announced by Arm on September 22, 2020.[6] It is said to be initially realized with a 7 nm process from TSMC. One of the changes from the X1 is that it supports SVE 2x256-bit.
According to The Next Platform, the AWS Graviton3 is based on the Neoverse V1.[7][8]
Neoverse V2
editNeoverse V2 (code named Demeter) is derived from the ARM Cortex-X3 and implements the ARMv9.0-A instruction set. It was officially announced by Arm on September 14, 2022.[9][10] NVIDIA Grace,[11] AWS Graviton4[12] and Google Axion[13] are based on the Neoverse V2.
Notable changes from the Neoverse V1:[14]
- BTB capacity: 12K entries
- TAGE predictor: 8-table
- micro-op cache: 1536 entries (reduced for efficiency)
- Decode width: 6
- Rename / Dispatch width: 8
- ROB: 320 entry
- Execution ports: 15
- L2 cache: 1024-2048?KB per core
- CMN-700 mesh interconnect
- Up to 256 cores per die
- Up to 512?MB SLC
- Up to 4?TB/s bandwidth
Neoverse V3
editNeoverse V3 (code named Poseidon) was teased by Arm alongside the V2 and E2 announcements.[15] It is targeted for systems including DDR5, PCIe gen6, and CXL 3.0. The codename Poseidon was first used for the generation succeeding Zeus, now V1, and targeted for 2021 on a 5nm node.[16]
Neoverse N-Series
editThe Neoverse N-Series processors are intended for core datacenter usage.
Neoverse N1
editOn February 20, 2019, Arm announced the Neoverse N1 microarchitecture (code named Ares) derived from the Cortex-A76 redesigned for infrastructure/server applications. The reference design supports up to 64 or 128 Neoverse N1 cores.[17][18]
Notable changes from the Cortex-A76:
- Coherent I-cache and D-cache with 4-cycle LD-use
- L2 cache: 512–1024?KB per core
- Mesh interconnect instead of 1–4 cores per cluster
Neoverse N1 implements the ARMv8.2-A instruction set.
The Ampere Altra (2-socket 80-core) and AWS Graviton2 (64-core) CPU platforms are based on Neoverse N1 cores and were released in 2020.[19]
Neoverse N2
editThe Neoverse N2 (code named Perseus) is derived from the Cortex-A710 and implements the ARMv9.0-A instruction set.[19] It was officially announced by Arm on September 22, 2020.[6] On August 28, 2023, Arm announced the Neoverse CSS N2 (Genesis), a customizable CPU subsystem implementation by Arm to reduce the time to market for customers.[20][21][22][23] Microsoft Azure Cobalt 100 128 Core CPU and Alibaba Yitian 710 use Neoverse N2.[24][25]
Notable changes from the Neoverse N1:[26][27]
- BTB capacity: 8K entries
- micro-op cache: 1536 entries
- Rename / Dispatch width: 5
- ROB: 160+ entry
- Pipeline depth: 10 cycles
- Execution ports: 13
- SVE2 support
- CMN-700 mesh interconnect
Neoverse N-Next
editNeoverse N-Next, presumably N3, was teased by Arm alongside the V2 and E2 announcements.[15] It is targeted for systems including DDR5, PCIe gen6, and CXL 3.0.
Neoverse E-Series
editThe Neoverse E-Series processors are intended for edge computing. They are designed for increased data throughput at decreased power consumption.
Neoverse E1
editNeoverse E1 is derived from the Cortex-A65AE[28] and implements the ARMv8.2-A instruction set. It support SMT.
Neoverse E2
editNeoverse E2 is derived from the Cortex-A510[15] and implements the ARMv9-A instruction set.
Neoverse E-Next
editNeoverse E-Next, presumably E3, was teased by Arm alongside the V2 and E2 announcements.[15] It is targeted for systems including DDR5, PCIe gen6, and CXL 3.0.
Matrix multiplication theoretical performance
edit| INT8 | BF16 | FP32 | FP64 | |
|---|---|---|---|---|
| Neoverse N1[29] | 64 | 32 | 16 | 8 |
| Neoverse N2[29] | 128 | 64 | 16 | 8 |
| Neoverse V1[29] | 256 | 128 | 32 | 16 |
| Intel 3rd Gen Xeon SP[30] | 256 | — | 64 | 32 |
| Intel 4th Gen Xeon SP[30] | 2048 | 1024 | 64 | 32 |
Successors
editWith code name Poseidon a successor for Neoverse V1 (aka Zeus)[31] was first publicly mentioned on TechCon 2018. Actual introduction (used by third party chip designers in their products) was given in form of a rough target date of 2021. Its initial realization process is said to be 5 nm by TSMC.
References
edit- ^ "Arm Neoverse".
- ^ "Arm Puts Some Muscle Into Future Neoverse Server CPU Designs". 27 April 2021.
- ^ "Neoverse V1 - Microarchitectures - ARM - WikiChip".
- ^ "Arm Announces Neoverse V1, N2 Platforms & CPUs, CMN-700 Mesh: More Performance, More Cores, More Flexibility". Archived from the original on May 17, 2021.
- ^ "Neoverse V1". Retrieved 2025-08-14.
- ^ a b "Accelerating the next generation cloud-to-edge infrastructure". Retrieved 2025-08-14.
- ^ "Inside Amazon's Graviton3 Arm Server Processor". 4 January 2022.
- ^ "Graviton 3: First Impressions". Chips and Cheese. 2025-08-14. Retrieved 2025-08-14.
- ^ "Redefining the global computing infrastructure with next-generation Arm Neoverse platforms".
- ^ "Neoverse V2". developer.arm.com. Retrieved 2025-08-14.
- ^ "NVIDIA Grace CPU and Arm Architecture". NVIDIA. Retrieved 2025-08-14.
- ^ "Join the preview for new memory-optimized, AWS Graviton4-powered Amazon EC2 instances (R8g)". AWS. Retrieved 23 December 2023.
- ^ "Introducing Google's new Arm-based CPU". Google Cloud Blog. Retrieved 2025-08-14.
- ^ "Hot Chips 2023: Arm's Neoverse V2". Chips and Cheese. 2025-08-14. Retrieved 2025-08-14.
- ^ a b c d "Arm Announces Neoverse V2 and E2: The Next Generation of Arm Server CPU Cores". Archived from the original on September 15, 2022.
- ^ Kennedy, Patrick (2025-08-14). "Arm Neoverse Brand Launched for Infrastructure Servers to Edge". ServeTheHome. Retrieved 2025-08-14.
- ^ Frumusanu, Andrei. "Arm Announces Neoverse N1 & E1 Platforms & CPUs: Enabling A Huge Jump In Infrastructure Performance". www.anandtech.com. Archived from the original on February 20, 2019. Retrieved 2025-08-14.
- ^ "Arm Launches New Neoverse N1 and E1 Server Cores". WikiChip Fuse. 2025-08-14. Retrieved 2025-08-14.
- ^ a b Frumusanu, Andrei. "Arm Announces Neoverse V1, N2 Platforms & CPUs, CMN-700 Mesh: More Performance, More Cores, More Flexibility". www.anandtech.com. Archived from the original on April 27, 2021. Retrieved 2025-08-14.
- ^ "Neoverse CSS Fastest Path to Production Silicon - Infrastructure Solutions blog - Arm Community blogs - Arm Community". community.arm.com. 2025-08-14. Retrieved 2025-08-14.
- ^ Ltd, Arm. "Neoverse Compute Subsystems". Arm | The Architecture for the Digital World. Retrieved 2025-08-14.
- ^ "Arm at HC35 (2023): CSS-Genesis". Chips and Cheese. 2025-08-14. Retrieved 2025-08-14.
- ^ Morgan, Timothy Prickett (2025-08-14). "Arm Gets Closer To Creating Full-Blown Server CPU Designs - The Next Platform". www.nextplatform.com. Retrieved 2025-08-14.
- ^ Lee, John (16 November 2023). "Microsoft Azure Cobalt 100 128 Core Arm Neoverse N2 CPU Launched". ServeTheHome. Archived from the original on 19 March 2024.
- ^ Yang, Willen (18 June 2024). "Accelerated LLM inference on Arm Neoverse N2". Arm Community Blogs. Archived from the original on 17 July 2024.
- ^ "ARM's Neoverse N2: Cortex A710 for Servers". Chips and Cheese. 2025-08-14. Retrieved 2025-08-14.
- ^ Frumusanu, Andrei. "Arm Announces Neoverse V1, N2 Platforms & CPUs, CMN-700 Mesh: More Performance, More Cores, More Flexibility". www.anandtech.com. Archived from the original on April 27, 2021. Retrieved 2025-08-14.
- ^ "Arm Announces Neoverse N1 & E1 Platforms & CPUs: Enabling a Huge Jump in Infrastructure Performance". Archived from the original on May 5, 2022.
- ^ a b c "Arm Announces Neoverse V1, N2 Platforms & CPUs, CMN-700 Mesh: More Performance, More Cores, More Flexibility". Archived from the original on May 17, 2021. Retrieved 2025-08-14.
- ^ a b "Accelerate Artificial Intelligence (AI) Workloads with Intel Advanced Matrix Extensions (Intel AMX)" (PDF). Intel. Retrieved 2025-08-14.
- ^ "Poseidon - Microarchitectures - ARM - WikiChip".